A DLL-based Clock Data Recovery with a modified input format

A 2.5-Gb/s DLL-Based Burst-Mode Clock and Data Recovery Circuit With 4× Oversampling

A 900 Mbit/s CMOS Data Recovery DLL using Half-Frequency Clock

A CMOS sub-circuit that is able to improve data communication is described. It removes jitter and hence improves the eye diagram of high-speed digital data signal. The circuit is based on a delay-locked loop and uses a half-frequency reference clock. The prototype circuit is fabricated in 2.5 V, 0.25-μm CMOS and occupies an area of only 270 x 50 μm. It is demonstrated that at 900 Mbit/s NRZ dat...

A Self Calibrated Based Clock Generator for DLL

In this paper, a Delay-Locked Loop (DLL) based clock generator is designed which can be used mainly for dynamic frequency scaling. This DLL-based clock generator is found to have low-jitter and can provide the system clock with frequencies in the range of 0.5 to 8 times of reference clock, depending on the workload of the EISC processor. This proposed analog self-calibration method and a phase ...

Design of Self Calibrated DLL Based Clock Generator Using Modified GDI Technique

This paper describes a low-jitter delay-locked loop (DLL)-based clock generator for dynamic frequency scaling in the extendable instruction set computing (EISC) processor. The DLL-based clock generator provides the system clock with frequencies of the reference clock, according to the workload of the EISC processor. The proposed self-calibration method and a phase detector with an auxiliary cha...

A CMOS Delayed Locked Loop ( DLL ) for Reducing Clock Skew

Under 500ps Yong-Bin Kim Tom Chen Department of Electrical Engineering Colorado State University Abstract This paper presents a variable delay line DLL circuit implemented in a 0.8 m CMOS technology. A phase detector and two charge pump circuits calibrate the delay per stage of the delay line using push-pull type clock synchronization scheme. The delay line can be programmed 6 to 18 stages. The...